Personal computers ("PCs") typically employ multiple components, such as: (i) a processor for processing commands, (ii) a memory array for temporarily storing data, (iii) input devices such as keyboards and mice for inputting user commands, (iv) output devices such as visual display devices and printers for providing an output of visual data to users, and (v) mass storage devices such as hard and floppy disk drives for permanently storing data. The components are intercoupled by a bus. A basic input/output system ("BIOS") and operating system ("OS") generally control basic operation of the processor, the other components, and their interaction therebetween via the bus. Upon such a platform, the PC can perform various software applications, such as word processing, spreadsheet, database and other applications.
As software applications become longer and more complex, the PC must provide increased speed and performance so that the applications can run efficiently and without undue delays. Since the various computer components communicate through and share the bus, and since no two components can seize the bus concurrently, the bus has caused delays. As more components are attached to the bus, a propagation delay through the bus increases as the components coordinate to use the bus. More importantly, the bus becomes a bottleneck as the need for greater amounts of data to transfer along the bus exceed the capacity, or bandwidth, of the bus. "Bandwidth" typically refers to the number of bits per unit time that can be transferred along the bus.
One solution to the bottleneck caused by the bus, and thereby a solution to need for faster PCs, has been to create multiple bus hierarchies. Under such hierarchies, two or more buses are employed in the PC. Typically, a local or processor bus couples the processor and the memory array. An expansion or input/output ("I/O") bus couples the input/output devices and mass storage devices, such as hard drives. The processor and I/O buses communicate with each other via a bus interface or controller coupled therebetween.
The processor bus has a high bandwidth and thus is able to rapidly transfer data between the processor and the memory array. The I/O bus performs slower data transfers, such as writing data to, or reading data from, a disk drive, transferring data to a video or printer card for outputting data to a display device or printer, or other operations involving input and output devices ("peripheral devices"). When the processor requires data from, e.g., the hard drive, the processor issues a command to an I/O controller, which in turn, communicates to the hard drive to read the requested data. When the hard drive outputs the data to the I/O controller, the I/O controller notifies the processor that the requested data is now available. Thereafter, the processor receives the data, via the I/O and processor buses, to perform operations on the data or write it to the memory array. Such a transfer of data, however, requires the active intervention of the processor to transfer the data between the hard drive and the memory array. Since the processor is involved with transferring data, it cannot perform other tasks, which ultimately slows the PC's performance.
To improve the PC's speed, direct memory access ("DMA") techniques arose that allowed large volumes of data to be moved without significant processor intervention. When the processor desires to read or write a block of data, it issues a command to a DMA module, with at least the following information: (1) whether a read or write is requested, (2) an address of the device on the I/O bus involved in the transfer (e.g., the hard disk drive), (3) a starting location or address in the memory array to read data from or write data to, and (4) a number of words or bytes to be read or written. The processor then identifies an address to write data to or read data from on the hard disk. Thereafter, the processor is free to perform other tasks.
Concurrently, the DMA module issues the appropriate read and write commands and addresses to transfer an entire block of data, one word at a time, directly from the memory array to the hard disk, or vise versa, without further involving the processor. Whenever possible, the DMA module exchanges data along the slower I/O bus, allowing the processor to freely use the processor bus. When the data transfer is complete, the DMA module sends an interrupt signal to the processor indicating that the transfer is complete. The processor typically then ensures that all data was transferred successfully. Thus, the processor is involved only at the beginning and end of the data transfer. The processor, however, still must be involved during the DMA transfer. If data from one hard disk is to be transferred to another hard disk, the data must first be transferred to the memory array under one DMA transfer. Thereafter, the data must be transferred from the memory array to the second hard disk under a second DMA transfer. The processor would thus be involved at least four times during such a transfer between hard disk drives. Such involvement by the processor necessarily slows the performance of the PC.
To further speed performance of the PC, computer designers have attempted to increase the performance of the hard disk drives, which perform considerably slower than the processor. As is known, hard disk drives and other I/O devices require an interface or controller to permit communication between the processor and the I/O device. To help speed performance of the hard disk drive, and therefore provide improved PC performance, a hard disk drive interface, known as the Integrated Drive and Electronics ("IDE") interface was developed. The IDE interface transfers data from a hard disk to a bus at a maximum rate of 5 megabytes per second, which is faster than previous disk drive interfaces. Nevertheless, if large amounts of data are to be transferred, e.g., from a hard disk drive to a tape drive, the 5 megabyte rate will slow a PC computer and require most of the memory array and bus bandwidth to perform such a transfer.
To help improve PC performance, particularly when data is exchanged under such a disk drive to tape drive transfer (typically as a back-up system for data archival purposes), one known system expedited this transfer using the IDE interface. In U.S. Pat. No. 5,446,877, a data archival device allowed data to be written to a tape drive coupled to an IDE interface, while data was read from a disk drive coupled to the interface. A software routine managed access to the tape drive, as well as controlled the tape drive to seize the IDE interface only during periods when information was being communicated over the interface. Such a system, however, required certain routines, buffers, and control electronics, within the tape drive, which can be expensive and limited for use with the tape drive. The disclosed system is unavailable for transferring data between hard drives. Additionally, the system still requires data from the disk drive to be transferred first to the memory array, and then to the tape drive, thereby requiring processor intervention, memory in the array and bus bandwidth.
While the system disclosed in the '877 patent had certain limitations, such as requiring certain control electronics in the tape drive, it nevertheless was adaptable for use with the standard IDE interface. The IDE interface provided enhanced PC performance, but it still was considerably slower than the speed of most processors. Additionally, the IDE interface could accommodate only two drives. Users soon required not only a hard disk drive and a tape drive, but also two or more hard disk drives and other storage devices, such as compact disk, read-only memory ("CD-ROM") drives, and so on. Many of these devices could transfer data at a rate much greater than the 5 megabytes per second limitation of the IDE interface.
Recently, enhanced IDE ("EIDE") has become available, which allows up to four devices to be connected thereto, two devices coupled along a primary IDE interface or bus, and two coupled along a secondary IDE bus. Each bus can operate at a maximum rate of 16 megabytes per second, or possibly greater. The EIDE interface also allows for large DMA data transfers. Under such DMA transfers, the EIDE interface seizes the I/O bus and operates as a "bus master," functioning like the processor, to thereby allow large blocks of data to be transferred to and from the hard disk drive to the memory array without processor intervention.
The details on DMA transfers performed by EIDE controllers is described in detail in Small Form Factors Committee document SFF-8038i. In general, under such a DMA transfer, the processor stores a physical region descriptor ("PRD") table in the memory array that includes one or more PRDs. The PRDs describe one or more areas of memory in the memory array used in the DMA data transfer. Under a "scatter/gather" mechanism, large blocks of data can be scattered to various locations in the memory array (each identified by a separate PRD), and then gathered again for transfer back to a hard disk drive.
While the EIDE interface provides improved DMA transfers between a hard disk drive and the memory array, the CPU, nevertheless, must be employed to create the multiple PRD entries in the PRD table. Moreover, if a transfer from one hard disk drive to another were required, the processor would be involved twice during the transfer, once during transfer from the first drive to the memory array, and then from the memory array to the second drive. Such a data transfer between hard disk drives would necessarily tax not only the I/O bus, but also the processor bus to which the memory array is coupled. Moreover, large amounts of memory in the main memory array are required for large data transfers.